Trends in the design and manufacture of microelectronic dies, or integrated circuits (ICs) are toward increasing miniaturization, circuit density, robustness, operating speeds and switching rates, while reducing power consumption and defects in the ICs. ICs are made up of a tremendous number (e.g., millions to hundreds of millions) of devices (e.g., transistors, diodes, capacitors, etc.), with each component being made up of a number of delicate structures, manufactured through a number of process steps. As IC manufacture technology continues to evolve and manufacturing of smaller sized components and more compact ICs become reality, the delicate structures likewise become smaller, more compact, and correspondingly, more delicate.
At 90- and 65-nanometer technology nodes and beyond, many (e.g., 10 or more) layers of conductor wires are required to interconnect the many smaller, more compact and more delicate structures in the ICs in accordance with the design specifications. (Note that these many layers of interconnect conductor wires are insulated by a dielectric layer in between them. Such a dielectric layer is called an interconnect dielectric layer, an inter-wire dielectric layer, or an inter-wire-layer dielectric layer, hereafter.) Consequently, increasingly smaller, more compact and more delicate features of the interconnect conductor wires are becoming essential to handle such formidable task in the design and manufacture of the ICs. However, the smaller, more compact and more delicate interconnect conductor wire features are beginning to interact with the IC manufacturing processes, causing product yield loss. Such phenomena include, but not limited to, the interaction between the interconnect conductor wire features and the planarization process of the interconnect conductor and dielectric layers, the interaction between the interconnect conductor wire features and the lithography process that defines the interconnect conductor wire features, and the interaction between the interconnect conductor wire features and the plasma involved interconnect dielectric deposition and etch process or the plasma-involved interconnect conductor etch process.
The interaction between the interconnect conductor wire features and the planarization process of the interconnect conductor and dielectric layers such as, but not limited to, the chemical-mechanical polish (CMP) process, can cause non-uniformity of the conductor wire and dielectric thickness due to the dishing on the conductor wire surface and the erosion on the dielectric surface. Such effect reduces thickness of the interconnect conductor and dielectric layers, thus increasing the conductor wire resistance and the dielectric capacitance which can cause significant timing delays in circuits. Since there can be up to ten or more interconnect conductor and dielectric layers in the 65-nanometer technologies and beyond, the accumulated effect of the non-uniformity of the interconnect conductor wire and dielectric thickness can be formidable after all interconnect conductor and dielectric layers receive the planarization process.
The interaction between the interconnect conductor wire features and the lithography process can cause the conductor wires either short or open. Such interaction may increase or decrease the width and also change the shape of the conductor wires which run through the circuits. The lithography process defines and forms the physical features of the transistor gates in circuits in the case of polysilicon interconnect wires. The change of the transistor gate length, width or shape can either reduce the on-state drive current or increase the off-state leakage of the transistors, thus degrading transistor performance and therefore the circuit or product performance and yield.
The interaction between the interconnect conductor wire features and the plasma-involved interconnect dielectric deposition and etch process or the plasma-involved interconnect conductor etch process can cause damage to transistor gate oxides via the plasma induced charging current. Degradation of the transistor gate oxides by such effect has become one of the serious transistor reliability concerns in the industry.
To improve manufacturing yield loss, manufacture-friendly layout design of the products (circuits that make products) has become increasingly important. To achieve a good layout design as such, understanding how the interconnect conductor wire features, such as the width, length, shape, spacing, density, pattern, etc. of the conductor wires, interact with the IC manufacturing tools and processes associated with the interconnect conductor and dielectric planarization process, the interconnect conductor lithography process, and the plasma-involved interconnect dielectric deposition and etch and the interconnect conductor etch process is the key.
To date, a thorough and complete understanding of such interaction has not been rendered yet, partly because a thorough and complete design covering the best possible scenarios of the interconnect conductor wire features in product circuits has not been realized.